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Showing posts from June, 2014

The highs and lows of UVM

I just read this article Accellera DAC 2014 Breakfast—What Engineers Really Think About UVM) . They hit a few interesting points. I'd like to add another few points that I think were missed in this discussion. The highs UVM helps the developer create reusable components (though I have seen UVM components and sequences written so badly, that it would've been impossible to reuse them without bringing in the whole kitchen-sync). Already mentioned in the article is the adoption of the vendors (a kind mention to Synopsys , navigating UVM hyper linked and filtered test logs is a big time save [I suppose other vendors have them too, just writing from experience]). The lows Vendor issues The register model: we need better support from vendors for creating a nice and easily extensible register model (Synopsys: ralgen sucks). uvm_reg_adapter: VIP vendors please provide a uvm_reg_adapter for your agents, at least a standard one that can be somehow be built upon. Code vi