Notes on verification

I just read this article Accellera DAC 2014 Breakfast—What Engineers Really Think About UVM) . They hit a few interesting points. I'd like to add another few points that I think were missed in this discussion. The highs UVM helps the developer create reusable components (though I have seen UVM components and sequences written so badly, that it would've been impossible to reuse them without bringing in the whole kitchen-sync). Already mentioned in the article is the adoption of the vendors (a kind mention to Synopsys , navigating UVM hyper linked and filtered test logs is a big time save [I suppose other vendors have them too, just writing from experience]). The lows Vendor issues The register model: we need better support from vendors for creating a nice and easily extensible register model (Synopsys: ralgen sucks). uvm_reg_adapter: VIP vendors please provide a uvm_reg_adapter for your agents, at least a standard one that can be somehow be built upon. Code vi

So after I described my troubles with the UVM register model's coverage in my previous post , I revisited the issue in a slightly different context and discovered the current solution was rather lacking. Register block coverage In the previous example, coverage was taken for a value written via the register model. You access the data provided by the sample method, so you don't need any visibility into the register model you're covering. But what happens if you want to cover a bunch of registers, say you want to sample the values of various registers by calling the sample_values method after configuring them. In this case you need to be able to access the register classes which you won't be able to do as you're in a wrapper class, and not in the register block class. Two possible solutions Define the sample function for the various covergroups to include values of multiple registers. In the sample_values function call the sample function with the required value